Integrated Circuit Design

Circuit Design Experience

The Mayo Clinic SPPDG team has over 35 years of integrated circuit (IC) design and test experience, which is now and has been for decades a significant strength of this group. We have designed over 400 ICs in a very large number of semiconductor technologies, including III-V compound semiconductors, bulk silicon CMOS, SiGe BiCMOS, and in silicon-on-insulator (SOI) CMOS.  Digital circuit designs have ranged from relatively simple adder and multiplexer circuits to complex signal processors and system support functions.  Analog circuits have included analog-to-digital converters (ADCs), direct digital synthesizers, transmit/receive circuits, equalizers, amplifiers, and mixers. Some circuits have been designed to evaluate an emerging transistor technology, while others are intended to implement a prototype system.

Because this research group was founded to develop the highest-possible-throughput signal processors for large-data-volume requirements, we have always concentrated on exploiting IC technologies that promised the ability to develop very high clock rate digital functions, and more recently, high-center-frequency analog and mixed-signal components. Beginning in 2001 we expanded our IC design capabilities to explore the opposite end of the power and performance spectrum by designing ICs for low power, low bandwidth and high-resolution battery powered monitoring applications.

IC Technology Experience

In the 1980’s we designed application specific ICs using gallium arsenide metal semiconductor (GaAs MESFET) technologies. A typical IC might contain 20,000-30,000 transistors operating at 0.5-1.0 GHz. In the early 1990’s we designed ICs using GaAs heterojunction bipolar transistor (HBT) technologies with transistor counts in the hundreds but operating at clock rates of 10-12 GHz. These ICs were ideal for use as high-speed counters, specialized multiplexers and demultiplexers, and so on.  Some of these ICs were intended only as “test chips” to validate the device technology while other ICs were incorporated into highly specialized signal processors and actually fielded.

Beginning in the mid-1990s CMOS device performance increased to a level that piqued our interest. Additionally, we were intrigued by nascent ability to integrate HBTs on the same wafer as the CMOS devices, in a fabrication process referred to as BiCMOS technology. Our initial design attempts to create high throughput BiCMOS ICs were conducted in collaboration with IBM Watson Research Center to exploit IBM’s emerging silicon-germanium (SiGe) BiCMOS technology (known then as “SiGe 5 HP”).

We have worked with successive generations of both IBM’s SiGe BiCMOS and silicon-on-insulator (SOI) CMOS technologies, SiGe 9HP and 32 nm SOI CMOS respectively. We have designed ICs in Tower Jazz’s SiGe technologies, selecting a particular fabrication process depending on the needs of the specific ICs being designed. The table below summarizes our IC technology experience.

Summary of IC Technology Experience

Technology	Dates	Circuit Types
90 nm SiGe 9HP	2011-Present	Analog, digital, mixed-signal
40 nm GaN	2019	Analog only
16 nm FinFET CMOS	2018-2019	Digital only
0.13 µm SiGe SBC13S4	2018	Analog only
0.18 µm SiGe SBC18H4	2015-2017	Analog only
0.15 µm GaN	2012-2015	Analog only
90 nm Bulk RF CMOS	2012-2014	Analog, digital, mixed-signal
0.13 µm Bulk RF CMOS	2011-2019	Analog, digital, mixed-signal
32 nm SOI CMOS	2010	Digital only
45 nm SOI CMOS	2009	Analog mixed-signal
65 nm Bulk CMOS	2006-2007	Analog, digital, and mixed-signal
0.18 µm SiGe SBC18HA	2005-2006	Analog mixed-signal
0.13 µm SiGe 8HP	2004-2012	Analog, digital, and mixed-signal
ABCS HBT	2004-2006	Digital only
ABCS HEMT	2003-2005	Analog only
0.18 µm SiGe SBC18HX	2003-2004	Analog mixed-signal
0.13 µm Bulk CMOS	2003	Analog and digital
InAs HEMT	2002-2003	Analog only
InP HEMT	2002	Analog and digital
GaAs HEMT	2001-2002	Analog and digital
0.18µm Bulk CMOS	2001	Digital only
0.25 µm SiGe 7HP	2000-2003	Analog, digital, and mixed-signal
0.25 µm Bulk CMOS	1999-2000	Analog and digital
0.18 µm SOI CMOS	2000-2003	Analog and digital
0.35 µm SOI CMOS	1999-2001	Analog and digital
0.5 µm SiGe 5HP	1997-1999	Digital only
InP HBT	1996-2003	Analog and digital
0.25 µm SOI CMOS	1995-1998	Digital only
0.5 µm Bulk CMOS	1995-1999	Digital only
GaAs HBT	1993-1999	Digital only
GaAs MESFET	1983-1995	Digital only

Examples of Mayo Clinic SPPDG Low-Power Mixed-Signal IC Design

Delta-Sigma Analog-to-Digital Converter

In support of a Mayo Clinic research laboratory we designed a four-channel 16-bit delta-sigma analog-to-digital converter (∆Σ ADC) designed for neurochemical and neuroelectrical measurements. The block diagram for the ∆Σ ADC appears in the following figure (Fig.1). 

To optimize the signal-to-noise ratio (SNR), each channel is implemented with a 128X oversampled continuous-time 3rd-order ∆Σ modulator with an input signal bandwidth of 50 kHz. The serial output of each modulator is processed by a digital low-pass filter and decimation filter that converts the serial data into 16-bit samples at a maximum rate of 100 kS/s. When monitoring low bandwidth signals the decimation filter can be programmed to apply additional decimation to reduce the output sample rate, by factors of two, down to 24.4 S/s.

To accommodate a range of input signal amplitudes each channel has eight selectable ranges for both neurochemical (± 1 uA to ± 8 uA) and neuroelectrical (± 6 mV to ± 48 mV) measurements. The IC also supports a high-resolution neurochemical input range of ± 31.25 nA. Configuration and control of the ∆Σ ADC IC is achieved through an I²C interface and the 16-bit data samples are output on an I²S interface.

The IC was fabricated in a IBM 0.13 µm CMOS 8RF technology and operates on 3.3 V and 1.2 V power supplies. The measured power consumption is 2.5 mW per channel when the modulators are clocked at 12.8 MHz. Note that the IC receives 25.6 MHz input clock that is divided-by-two to generate 12.8 MHz on-chip with a 50% duty cycle. The IC measures 4.0 mm x 3.4 mm, as shown in the next figure (Fig.2).

Low-Power 4.6 GHz Voltage-Controlled Oscillator

Mayo Clinic SPPDG was tasked by DARPA to design low-power electronics to reduce power and area in Chip-Scale Atomic Clocks (CSACs) for battery powered applications. The first circuit was a low-power voltage-controlled oscillator (VCO) with a center frequency of 4.6 GHz to replace a commercial-off-the-self (COTS) VCO and multiple passive components used for an attenuator network. The second circuit was a low-power fractional-N synthesizer (discussed in the next section).

The VCO IC design integrated a custom VCO with attenuation circuitry on-chip using IBM’s 0.13 µm SiGe 8HP BiCMOS, as depicted in the next figure (Fig.3). Several support circuits are required for proper operation of the VCO in the CSAC system, including electrically programmable fuses (eFuses) to permanently store coarse frequency and VCO bias current settings, a power-on reset circuit to automatically sense the fuse settings after cycling power, and devices to protect sensitive FETs from electrostatic discharge (ESD).

In a prior CSAC system designed by a commercial supplier, the COTS VCO and passive attenuator components occupied 190 mm² of circuit board space and consumed over 25 mW of power. The Mayo-designed IC is packaged in a 4 mm x 4 mm quad-flat no-lead (QFN) package that occupies 16 mm² of circuit board space and consumes 8.3 mW of power, resulting in area reduction of over 90% and an approximate power savings of 67%.

4.6 GHz Radio Frequency Fractional-N Synthesizer Design

As part of a continuing effort to evolve low-power electronics to reduce power and area for CSAC systems, we designed a programmable fractional-N synthesizer IC. The goal of this design was to integrate a VCO, synthesizer circuitry, and a loop filter on the same IC. The fractional-N synthesizer circuitry is primarily a digital function requiring standard cell logic gates. To optimize power consumption for the synthesizer function we selected IBM 90 nm CMOS 9RF technology for the IC. The chip plot and die photograph appear in the next figure (Fig.4).

In the prior CSAC system described above, the original VCO, passive components, and synthesizer circuitry occupied > 220 mm² of circuit board space and consumed over 43 mW of power. The Mayo-designed synthesizer IC is packaged in a 4 mm x 4 mm quad-flat no-lead (QFN) package that occupies 16 mm² of board area and consumes 12.2 mW of power, resulting in an area reduction of over 92% and an approximate power saving of 72%.

2 GHz Radio Frequency Transceiver Design

The final example of a low-power mixed-signal IC is a proof-of-concept radio frequency transceiver. The transceiver operates by receiving commands from an incoming 2 GHz BPSK signal to control the operation of the transmitter. The receiver combines both analog and digital circuitry. Analog circuitry mixes down the incoming 2 GHz signal to a lower frequency that is then sent to the digital detector. The digital detector, implemented with approximately 40,000 logic gates, decodes the incoming BPSK signal to extract the commands for the transmit circuitry. The carefully executed design of the digital detector allows the transceiver to exhibit a receive sensitivity of -110 dBm.

The transceiver is implemented in IBM 0.13 µm SiGe 8HP BiCMOS technology, presented in the next figure (Fig.5). The die size is 5 mm by 5 mm, with an approximate power consumption of 1.0 mW in idle mode and 1.3 mW in transmit mode.

Examples of Mayo Clinic SPPDG High Performance Design

20 Gb/s SerDes Transmitter with Tunable Output Impedance

In the 2006-2008 timeframe Mayo Clinic SPPDG initiated an investigation of novel circuit architecture techniques to increase the throughput of serializer/deserializer (SerDes) data transmitters. At that time open-literature publications reported data rates of 8.5-12 Gb/s for SerDes transmitters implemented in 65 nm bulk CMOS technologies. We reviewed multiple transmitter topologies and learned that source-series terminated (SST) transmitters were known to offer lower power solutions for SerDes signal transmission. To prove the concept we designed a SST transmitter to validate that level of performance with actual hardware, using IBM 65 nm CMOS 10SF technology.

The transmitter is a mixed-signal design using custom analog circuits, standard cell logic gates, and custom logic gates. The SST output drivers require true and complement data signals to be generated with accurate timing between them; this capability can be achieved with standard cell logic but consumes a large amount of power and limits speed. To minimize power consumption and maximize speed we designed custom complementary pass-gate logic (CPL) latches to remove the skew from the standard cell logic. Another important metric for SerDes transmitters is size (the smaller the SerDes, the more that can be packed along the edges of the IC); our design occupies 0.025 mm² and is shown in the next figure (Fig.6). Measured hardware operated at 20 Gb/s, consumed 8.3 mW/Gb/s, with output impedance adjustable from 45-55 ohms.

X-Band (10 GHz) Mixer

Mayo Clinic SPPDG was funded by DARPA to explore Gallium Nitride (GaN) IC technologies for the design of very high linearity mixers. GaN transistors are known for their high-speed switching characteristics and their ability to handle high power. We were requested to design and characterize an X-Band (10 GHz) mixer using GaN transistors. Mixers are commonly used in the receiver and transmitter sections of RF transceivers. Linearity is a critical metric for mixers; in the receive circuitry, poor linearity can result in interference from adjacent RF channels; while for the transmit circuitry, poor linearity can result in signal distortion that interferes with adjacent channels and limits maximum output transmit power. Our IC mixer design employed a double balanced resistive Quad FET mixer topology to maximize linearity. The design was implemented in TriQuint’s 0.15 µm GaN technology and achieved an Output IP3 (OIP3) of 21.5 dBm and an Input IP3 (IIP3) of 39 dBm. The die measures 4 mm x 4 mm and is mounted to a copper-tungsten plate, as illustrated in the next figure (Fig.7).

20 GS/s 5-bit Flash Analog-to-Digital Converter

In this example explored analog-to-digital circuit (ADC) topologies to maximize their speed and performance while minimizing power consumption. Our goal was a 5-bit flash ADC with a sampling rate of at least 20 GS/s using IBM 0.13 µm SiGe 8HP BiCMOS technology.

To reduce total power consumption we designed a completely new comparator architecture with an exclusive-or (XOR) function, using interleaved Gray-coded logic operating at a high clock rate. This approach reduced the number of logic circuits by a factor of two in comparison to a traditional 5-bit flash ADC architecture. We achieved an input bandwidth of 20 GHz through the use of a low-impedance input driver. The high-speed sampling was implemented with CML logic, and a 30 ohm clock driver connected to a clock tree network constructed of four equal 120 ohm differential branches.

The size of the resulting ADC IC is 3.5 mm x 3.5 mm, as presented in the next figure (Fig.8). The measured hardware achieved a maximum sampling rate of 35 GS/s with an input bandwidth of more than 20 GHz. Total power consumption was 4.8 W; we estimated that the XOR comparator and half-rate Gray-coded logic saved approximately 1.5 W.

Ka-Band (35 GHz) Low Noise Amplifiers

In the previous examples we discussed circuits designed in bulk CMOS, SiGe BiCMOS and GaN technologies. Here we present the design of two Ka-Band (35 GHz) Low Noise Amplifiers (LNAs) and a Ka-Band RF Switch using MIT Lincoln Laboratory’s 0.18 µm fully depleted silicon-on-insulator (SOI) CMOS technology, as shown in the next figure (Fig.9). The resulting chip also included device characterization structures used to measure the performance of individual transistors to allow device models to be created for this particular process.

 

Information updated Wednesday, July 12, 2023 ⋀ Back to top